# Arithmetic Micro-operations

Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

The basic arithmetic microoperations are addition, subtraction, increment, decrement, and shift. Arithmetic shifts are explained later in conjunction with the shift microoperations The arithmetic microoperation defined by the statement

R3 <- R1+R2

It specifies an add microoperation. It states that the contents of register R1 are added to the contents of register R2 and the sum transferred to register R3. To implement this statement with hardware we need three registers and the digital component that performs the addition operation. The other basic arithmetic microoperations are listed in Table . Subtraction is most often implemented through complementation and addition. Instead of using the minus operator, we can specify the subtraction by the following statement:

R3<-R1+R2’+1

R2’ is the 1’s complement of R2, Adding 1 to the 1’s Complement produces the 2’s Complement form. Adding the R1 to the 2’s complement of R2 is equivalent to R1-R2.

The increment micro operation is symbolized by plus one.the decrement micro operation  is symbolized by minus 1.these two micro operations are implemented with the help of combinational circuit.

Multiplication and Division  operations are valid arithmetic operations but are not included in the basic set of microoperations so these are not specified in the above table . Division is implemented with a sequence of subtract and shift microoperations. the multiplication operation is implemented with a sequence of add and shift microoperations. The only place where these operations can be considered as microoperations is in a digital system, where they are implemented by means of a combinational circuit.

A Binary Adder is a digital circuit that performs the sum of any two binary numbers with any length.

A Binary Adder is constructed using full-adder circuits connected in series, with the output carry from one full-adder connected to the input carry of the next full-adder.

The be;ow diagram represents the four full-adder circuits to provide a 4-bit binary adder.

The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the low-order bit.

The carries are connected in a chain through the full-adders. The input carry to the binary adder is C0 and the output carry is C4. The S outputs of the full-adders generate the required sum bits.

An n-bit binary adder requires n full-adders. The output carry from each full-adder is connected to the input carry of the next-high-order full-adder.

The n data bits for the A inputs come from one register (such as R1), and the n data bits for the B inputs come from another register (such as R2).

The sum can be transferred to a third register or to one of the source registers (R 1 or R2), replacing its previous content.

The Subtraction micro-operation can be done easily by taking the 2's compliment of addend bits and adding it to the augend bits.

The addition and subtraction operations can be combined into one common circuit by including an exclusive-OR gate with each full-adder.

The mode input M controls the operation. When M = 0 the circuit is an adder and when M = 1 the circuit becomes a subtractor.

The exclusive-OR gate connected in series receives input M and one of the inputs B.

When M is equel to 0, we have B⊕ 0 = B.

The full-adders receive the value of B, the input carry is 0, and the circuit performs A plus B.

When M is equal to 1, we have B⊕ 1 = B' and C0 = 1.

The B inputs are complemented, and a 1 is added through the input carry. The circuit performs the operation A plus the 2's complement of B.

## Binary Incrementer:

The increment microoperation adds one to a number in a register. For example, if a 4-bit register has a binary value 0100, it will go to 0101 after it is incremented.

This microoperation is easily implemented with a binary counter.

The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-adder.

The circuit receives the four bits from A0 through A3, adds one to it, and generates the incremented output in S0 through S3.

The circuit can be extended to an n-bit binary incrementer by extending the diagram to include n half-adders. The least significant bit must have one input connected to logic-1. The other inputs receive the number to be incremented or the carry from the previous stage.

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